`timescale 1ns / 1ps

module tb_xpmRom();

parameter A_WIDTH = 4;
parameter D_WIDTH = 6;
localparam MEM_SIZE = (1 << A_WIDTH) * D_WIDTH;

reg         clk;
reg         rst;
reg         en;
reg  [A_WIDTH-1:0]  addr;

wire [D_WIDTH-1:0]  dout;

// Tcl command:
// set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
xpm_memory_sprom #(
   .ADDR_WIDTH_A(A_WIDTH),          // DECIMAL
   .AUTO_SLEEP_TIME(0),             // DECIMAL
   .ECC_MODE("no_ecc"),             // String
   .MEMORY_INIT_FILE("testmem.mem"),// String
   .MEMORY_INIT_PARAM(""),          // String
   .MEMORY_OPTIMIZATION("true"),    // String
   .MEMORY_PRIMITIVE("auto"),       // String: auto, block, distributed, ultra 
   .MEMORY_SIZE(MEM_SIZE),          // DECIMAL
   .MESSAGE_CONTROL(0),             // DECIMAL
   .READ_DATA_WIDTH_A(D_WIDTH),     // DECIMAL
   .READ_LATENCY_A(3),              // DECIMAL
   .READ_RESET_VALUE_A("0"),        // String
   .USE_MEM_INIT(1),                // DECIMAL
   .WAKEUP_TIME("disable_sleep")    // String
)
xpm_memory_sprom_inst (
   .dbiterra(),                     // 1-bit output: Leave open.
   .douta(dout),                    // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
   .sbiterra(),                     // 1-bit output: Leave open.
   .addra(addr),                    // ADDR_WIDTH_A-bit input: Address for port A read operations.
   .clka(clk),                      // 1-bit input: Clock signal for port A.
   .ena(en),                        // 1-bit input: Memory enable signal for port A. Must be high on clock
                                    // cycles when read operations are initiated. Pipelined internally.

   .injectdbiterra(1'b0),           // 1-bit input: Do not change from the provided value.
   .injectsbiterra(1'b0),           // 1-bit input: Do not change from the provided value.
   .regcea(1'b1),                   // 1-bit input: Do not change from the provided value.
   .rsta(rst),                      // 1-bit input: Reset signal for the final port A output register stage.
                                    // Synchronously resets output port douta to the value specified by
                                    // parameter READ_RESET_VALUE_A.

   .sleep(1'b0)                    // 1-bit input: sleep signal to enable the dynamic power saving feature.
);

always #5 clk = ~clk;

integer i, j;
integer dice;
initial
begin
    clk = 0;
    rst = 1;
    #20;
    rst = 0;
    #10;
    for (i = 0; i < 16; i = i + 1) begin
        en = 0;
        dice = {$random()} % 3;
        for (j = 0; j < dice; j = j + 1) begin
            #10;
        end
        addr = i;
        en = 1;
        # 10;
    end
    en = 0;
    addr = 0;
    # 50;
    $display("Done.");
    $stop;
end

endmodule
